NDLI: Reconfigurable architecture for IP peripherals

Content Provider	IEEE Xplore Digital Library
Author	Saxena, M.K. Bhatnagar, E. Jaiswal, N. Parab, M. Kulkarni, S.N.
Copyright Year	2010
Description	Author affiliation: Wipro Technologies, Bangalore, India - 560100 (Kulkarni, S.N.) \|\| System LSI Division, Device Solutions Lab, Samsung India Software Operations, Bangalore, India - 560052 (Saxena, M.K.; Bhatnagar, E.; Jaiswal, N.; Parab, M.)
Abstract	A SoC typically integrates multiple peripheral IPs. Each one of these IP's has its own interfaces and integration requirements. The test benches designed for these IP's are different and require independent porting of test-cases on the SoC, thereby extending the test time. Also, practically there may not exist any use case that requires all these IPs at the same time. In this paper we propose a novel reconfigurable architecture concept to integrate multiple IPs on a single recon-figurable IP. This concept is applied to implement multiple serial and audio interface applications on a single IP. We also propose a methodology to integrate similar audio and serial interfaces onto a single reusable architecture. The architecture features multiple configurable blocks which are reconfigured and re-arranged to perform as any one of the serial or audio peripherals. The proposed architecture is AMBA compliant and special attention has been given to ensure an ease of SoC integration.
Starting Page	347
Ending Page	350
File Size	799901
Page Count	4
File Format	PDF
ISBN	9781424453078
e-ISBN	97883904742
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-07
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Silesian Univ of Technology
Subject Keyword	APB (AMBA Peripheral Bus) Protocols SFR (Special Function Registers) UART (Universal Asynchronous Receiver/Transmitter) I2S (Inter-IC Sound) Bus Data processing PCM (Pulse code modulation) Synchronization I2C (Inter-IC) Bus RXCLKCON (Receive Clock Configuration SFR) TXCLKCON (Transmit Clock Configuration SFR) Computer architecture PSV (Pre Scalar Value) Hardware SPI (Serial Peripheral Interface) IP networks System-on-a-chip MPSI (MultiProtocol Serial Interface) IrDA (Infrared Data Association) AC'97 (Intel's Audio Codec 97) DPR (Drift Corrector, Pulse Shaper, Recovered Data SFR)
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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