NDLI: Packet selection technique for clock recovery over packet networks

Content Provider	IEEE Xplore Digital Library
Author	Chaloupka, Z. Alsindi, N. Aweya, J.
Copyright Year	2014
Description	Author affiliation: Etisalat BT Innovation Centre, Khalifa Univ. of Sci., Technol. & Res., Abu Dhabi, United Arab Emirates (Chaloupka, Z.; Alsindi, N.; Aweya, J.)
Abstract	The primary challenge in the design of a clock recovery system for packet networks is to deal with Packet Delay Variations (PDVs) - that is, the variation of the packet transit delays introduced by queuing process in Network Elements (NEs) such as switches and routers. In order to obtain clean signal from recovered clock various techniques are employed to mitigate the effect of the PDVs. One of such mechanisms, referred to as Packet Selection Algorithm (PSA), reduces recovered clock noise variance by filtering incoming timing packets in such a way that only packets complying with predefined selection criteria are passed to the clock recovery algorithm. Since it is a non-trivial task to find optimal PSA criteria analytically using output variance minimization, this paper introduces a probabilistic approach for the PSA optimality analysis. Based on this probabilistic analysis a new packet selection technique is proposed, which outperforms prior art when compared in simulation by means of Time Deviation (TDEV) standardized metric.
Sponsorship	IEEE Instrum. Meas. Soc.
Starting Page	108
Ending Page	111
File Size	1629132
Page Count	4
File Format	PDF
e-ISBN	9781479926992
DOI	10.1109/ISPCS.2014.6948701
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	clock recovery frequency synchronization packet delay variation Probabilistic logic Stability analysis Delays Synchronization packet selection Clocks
Content Type	Text
Resource Type	Article

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