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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kaiyu Wang Zhenan Tang Tao Ge Hualong Li |
| Copyright Year | 2011 |
| Abstract | According to the structure and principle of PLL (Phase-Locked Loop) and system's stability, capture range and lock-up time, the VCO unit is designed. Based on 0.5µm CMOS mixed signal technology, Hspice is used to design and simulate the circuit. After designing the layout, Calibre is used to extract parasitic parameter and analyze the result of post-simulation. Applying the VCO (Voltage Controlled Oscillator) can realize the function of digital PLL and it also can be used as an independent IP hard core in the clock recovery of communication systems and frequency synthesis of digital system. |
| Starting Page | 749 |
| Ending Page | 752 |
| File Size | 409568 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781612842899 |
| DOI | 10.1109/ICICTA.2011.474 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-03-28 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Frequency synthesizers Voltage-controlled oscillators Layout simulation design CMOS digital phase-locked loops Indexes Synchronization Phase locked loops voltage-controlled oscillator |
| Content Type | Text |
| Resource Type | Article |
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