NDLI: Design studies on the implementation of On Board Control, Signal Acquisition and Communication (OBCSAC) system on FPGA/ASIC platforms

Content Provider	IEEE Xplore Digital Library
Author	Balaji, V. Ramakrishna, P.V.
Copyright Year	2007
Description	Author affiliation: Dept. of ECE, Anna Univ., Chennai (Balaji, V.; Ramakrishna, P.V.)
Abstract	The on board control, signal acquisition and communication (OBCSAC) subsystem is a critical component of all satellite systems. This paper presents the results of a feasibility study on realizing the design subsystem first on FPGA, and then on ASIC. Apart from giving the design details and results on a typical basic configuration, a number of extensions of this architecture have been studied and the results are presented. Specifically, starting from the realization of the basic configuration on a commercial antifuse FPGA, the studies carried out include (a) mapping the vital configuration onto an equivalent radiation hardened antifuse FPGA (b) mapping the same configuration onto a commercial FPGA after incorporating dasiaTriple Modular Redundancy (TMR) manually at the RTL level, (c) altering the basic architecture significantly to conform to the CCSDS standard prescribed for the OBCSAC of any satellite and mapping the design onto to FPGAs as well as on ASICS first without TMR and then separately incorporating TMR for each case. The basic configuration realized in an FPGA had been extensively tested in hardware under various expected environmental conditions and the FPGA utilization details are provided. For the ASIC design, the details up to the layout/GDSII stage are presented. Further, in the case of the ASIC, the test patterns for the netlist were generated based on ATPG software and the details of fault coverage are provided. The FPGA designs were carried out with Actel SX72A and AX1000 device families and the ASIC designs were carried out using the AMIS 0.35u CMOS libraries. The results presented in this work will serve as a design guideline in terms of FPGA/ASIC area, power, speed, and fault coverage and fault tolerance to those working in the area of system design.
Starting Page	1340
Ending Page	1344
File Size	265960
Page Count	5
File Format	PDF
ISBN	9781424413553
DOI	10.1109/ICIAS.2007.4658602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-25
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Satellites FPGA TMR Encoding Tunneling magnetoresistance ASIC Design Telemetry CCSDS Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design and implementation of ASIC for weather monitoring application using FPAA and FPGA

Synthetical analysis on space radiation tolerance techniques in ASICs and FPGAs

Implementation of CCSDS based imaging satellite packet processing unit on FPGA hardware

VME Bus Interface Circuit Design and Its ASIC Implementation

Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication

Dependability Issues of INPE's ESA/CCSDS Telecommand/Telemetry Subsystem

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition

Design studies on the implementation of On Board Control, Signal Acquisition and Communication (OBCSAC) system on FPGA/ASIC platforms

Similar Documents

Design and implementation of ASIC for weather monitoring application using FPAA and FPGA

Synthetical analysis on space radiation tolerance techniques in ASICs and FPGAs

Implementation of CCSDS based imaging satellite packet processing unit on FPGA hardware

VME Bus Interface Circuit Design and Its ASIC Implementation

Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication

Dependability Issues of INPE's ESA/CCSDS Telecommand/Telemetry Subsystem

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Design and Implementation of a Preprocessing Circuit for Bandpass Signals Acquisition

Design studies on the implementation of On Board Control, Signal Acquisition and Communication (OBCSAC) system on FPGA/ASIC platforms