NDLI: Hardware performance estimation by dynamic scheduling

Content Provider	IEEE Xplore Digital Library
Author	de Aledo Marugan, P.G. Gonzalez-Bayon, J. Espeso, P.S.
Copyright Year	2011
Description	Author affiliation: Dpto de Microelectrónica, Universidad de Cantabria, Santander (Cantabria), Spain (de Aledo Marugan, P.G.; Gonzalez-Bayon, J.; Espeso, P.S.)
Abstract	Hardware/software partition is an essential step in current complex digital design. During the last decades, several partition methodologies have been proposed, most of them based on software and hardware performance estimations. A common limitation of these methodologies is that the source code of the hardware part has to be modified and/or adapted in order to obtain accurate hardware estimations. This paper presents a new hardware performance estimation tool that works with high-level system specifications. An important advantage of the proposal is that the same source code can be used for hardware and software estimations. In order to obtain the execution time of the hardware partition during system simulation, every element of the algorithm is decomposed into primitive operations that are dynamically queued in a sliding-window of limited size. Several hardware-related restrictions are applied to this queue and two dynamic scheduling methodologies are used. The first scheduling methodology enables the estimation of a low bound of the hardware execution time. This estimation should be faster than any implementation of the hardware part. The second methodology provides an upper limit of the execution time that represents a hardware implementation with a low synthesis effort. These limits help designers to decide if it worthwhile to adapt part of the code to be implemented in hardware.
Starting Page	1
Ending Page	6
File Size	760755
Page Count	6
File Format	PDF
ISBN	9781457707636
ISSN	16369874
e-ISBN	9782953050448
e-ISBN	9782953050431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-13
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	ECSI
Subject Keyword	Algorithm design and analysis estimation Software algorithms Estimation scheduling Dynamic scheduling Hardware Software dynamic Registers
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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