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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jahre, M. Grannaes, M. Natvig, L. |
| Copyright Year | 2009 |
| Abstract | The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the nature of memory system interference is vital to achieve good fairness/complexity/performance trade-offs in CMPs. Our goal in this work is to quantify the latency penalties due to interference in all hardware-controlled, shared units (i.e. the on-chip interconnect, shared cache and memory bus). To achieve this, we simulate a wide variety of realistic CMP architectures. In particular, we vary the number of cores, interconnect topology, shared cache size and off-chip memory bandwidth. We observe that interference in the off-chip memory bus accounts for between 63% and 87% of the total interference impact while the impact of cache capacity interference can be lower than indicated by previous studies (between 5% and 32% of the total impact). In addition, as much as 11% of the total impact can be due to uncontrolled allocation of shared cache Miss Status Holding Registers (MSHRs). |
| Starting Page | 622 |
| Ending Page | 629 |
| File Size | 317345 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424446001 |
| DOI | 10.1109/HPCC.2009.77 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-06-25 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Information science High performance computing Interference Computer architecture Bandwidth Hardware Topology System-on-a-chip Resource management Delay |
| Content Type | Text |
| Resource Type | Article |
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