NDLI: A high-performance heterogeneous embedded signal processing system based on serial RapidIO interconnection

Content Provider	IEEE Xplore Digital Library
Author	Wu Changrui Cen Fan Cai Huizhi
Copyright Year	2010
Description	Author affiliation: Institute of Acoustics, Chinese Academy of Sciences, Beijing, 100190, China (Wu Changrui; Cen Fan; Cai Huizhi)
Abstract	The demand for high-performance embedded signal processing systems has expanded rapidly in recent years. As applications requiring faster computation capability, higher throughput bandwidth and more flexible interconnection, traditional embedded signal processing systems could not meet the demand of ever-increasing performance. The paper designs a high-performance heterogeneous embedded signal processing system based on the serial RapidIO interconnection to fulfill the next generation radar system. The system is designed based from aspects of computation capability of single processor, scale of parallelism in system, arrangement of memory architecture, interconnection topology and bandwidth. The system consists of three modules which are high-speed AD module, heterogeneous processing module including FPGA and CPU and RapidIO switch module. The system conform to Advanced Mezzanine Card (AMC) Standard and AdvancedTCA Standard and all modules aggregated by serial RapidIO. The system can perform up to 2Gsps sampling rate, up to 550MHz processing capability on FPGA and 1.5GHz on CPU and up to 80Gbits/s aggregate bandwidth. And finally applications such as system dataflow and control are presented.
Starting Page	611
Ending Page	614
File Size	501466
Page Count	4
File Format	PDF
ISBN	9781424455379
e-ISBN	9781424455409
DOI	10.1109/ICCSIT.2010.5564987
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	high-performance heterogeneous computing Switches Information filters RapidIO interconnection Registers Field programmable gate arrays
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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