NDLI: An advanced H.264/AVC CAVLC decoding architecture for low power implementation

Content Provider	IEEE Xplore Digital Library
Author	Byung-Yup Lee Kwang-Ki Ryoo
Copyright Year	2010
Description	Author affiliation: Department of Information and Communication Engineering, Hanbat National University, Daejeon, Korea (Byung-Yup Lee; Kwang-Ki Ryoo)
Abstract	This paper proposes a VLSI design of CAVLC decoder used in H.264/AVC. The previous CAVLC hardware decoders are inefficient architectures due to some reasons. Firstly, they contain unnecessary decoding cycle. Secondly, they have limitation for a decoding capability, that is made by flush unit and increase hardware cost. Then we propose the two methods to improve performance and implement a low power design. One is a method that eliminates unnecessary decoding cycle. The other is a method that uses the extended barrel shifter. The experimental result shows that the proposed architecture needs only 68 cycles in average for one macroblock decoding and this architecture improves the performance by about 45% comparing with the previous designs. It can be run under lower operating frequency than previous ones and it consumes lower power than previous ones. The synthesis result shows that the design achieves the maximum operating frequency at 125 MHz and the hardware cost is about 12.6K under a 0.18um CMOS process.
Starting Page	484
Ending Page	487
File Size	759142
Page Count	4
File Format	PDF
ISBN	9781424476718
e-ISBN	9788988678268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-16
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	AICIT
Subject Keyword	CAVLC VLSI Pipelines Low Power Switches Logic gates Mobile communication Hardware Decoding H.264/AVC VLC
Content Type	Text
Resource Type	Article

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