NDLI: Second-order single channel digital tanlock based phase-locked loop

Content Provider	IEEE Xplore Digital Library
Author	Al-Ali, O.A. Anani, N. Al-Qutayri, M. Al-Araji, S. Ponnapalli, P.
Copyright Year	2012
Description	Author affiliation: College of Engineering, Khalifa University, Sharjah Campus, UAE (Al-Qutayri, M.; Al-Araji, S.) \|\| School of Engineering, Manchester Metropolitan University, UK (Al-Ali, O.A.; Anani, N.; Ponnapalli, P.)
Abstract	The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector of the proposed system so as to optimize the acquisition time and/or the lock range of the loop. The system performance evaluation results show that it is possible to selectively optimize certain parameters of the system in order to match specific application requirements.
Starting Page	1
Ending Page	4
File Size	382385
Page Count	4
File Format	PDF
ISBN	9781457714726
e-ISBN	9781457714733
DOI	10.1109/CSNDSP.2012.6292685
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-18
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Time frequency analysis Educational institutions Synchronization Phase locked loops Digital filters Frequency control
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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