NDLI: Self-timed shared division and square-root implementation using full redundant signed digit numbers

Content Provider	IEEE Xplore Digital Library
Author	Young-Sang Lee Jun-Woo Kang Lee-Sup Kim Seung-Ho Hwang
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea (Young-Sang Lee)
Abstract	A radix-2 square root implementation for self-timed dividers using redundant signed-digit (RSD) adders is presented. In this method, two self-timed RSD adder stages are used for each result bit selection. A very efficient and simple result bit selection logic compared to the previous designs is implemented by using double self-timed ring stages. The F-term in the RSD format is easily applied to two self-time substages. F-term generation is overlapped with a partial remainder calculation and result-bit selection. This makes the hardware implementation of the F-term generation much easier and less time-constraint. No additional time delay is included in the square-root arithmetic. From the SPICE simulation at 35/spl deg/C and under MOSIS 1.2 /spl mu/m design rule, the speed of this design is estimated to be 124 ns for 54 bit square-root and division calculation.
Starting Page	541
Ending Page	544
File Size	297869
Page Count	4
File Format	PDF
ISBN	0780357272
DOI	10.1109/ICVC.1999.820995
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-26
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay effects SPICE Hardware Logic design Iterative methods Proposals Equations Arithmetic Clocks Propagation delay
Content Type	Text
Resource Type	Article

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