NDLI: A VLSI-friendly ART1 neural algorithm and its CMOS analog current-mode implementation

Content Provider	IEEE Xplore Digital Library
Author	Serrano, T. Linares-Barranco, B. Huertas, J.L.
Copyright Year	1994
Description	Author affiliation: Dept. of Analog Design, Nat. Microelectron. Center, Seville, Spain (Serrano, T.)
Abstract	We describe a modification to the original ART1 algorithm that is conceptually similar, can be implemented in hardware with less sophisticated components, and presents the same computational capabilities. We present a prototype chip for this modified ART1 algorithm fabricated in a standard low cost 1.5 /spl mu/m double-metal single-poly CMOS process. It has a die area of 1 cm/sup 2/ and is mounted in a 120-pin PGA package. The chip implements an ART1 network with 100 F1 nodes and 18 F2 nodes. It can therefore cluster 100 binary pixels input patterns into up to 18 different categories. Modular expandability of the system is possible by assembling an N/spl times/M array of chips without any extra interfacing circuitry, resulting in an F1 layer with 100/spl times/N nodes, and an F2 layer with 18/spl times/M nodes. Pattern classification is performed in less than 1 /spl mu/s, which means an equivalent computing power of 1.8/spl times/10/sup 9/ connections per second.
Starting Page	405
Ending Page	412
File Size	1021971
Page Count	8
File Format	PDF
ISBN	0818667109
DOI	10.1109/ICMNN.1994.593736
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-26
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonlinear equations Subspace constraints Differential algebraic equations Prototypes Clustering algorithms Differential equations Computer architecture Hardware Steady-state Microelectronics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in