NDLI: Array processor featuring an effective FIFO-based data stream management

Content Provider	IEEE Xplore Digital Library
Author	Miyazaki, T. Nomoto, Y. Sato, Y. Sedukhin, S.G.
Copyright Year	2008
Description	Author affiliation: Grad. Sch. of Comput. Sci. & Eng., Univ. of Aizu, Fukushima (Miyazaki, T.; Nomoto, Y.; Sato, Y.; Sedukhin, S.G.)
Abstract	In array processors, data I/O management is the key to realizing high-speed matrix operations that are often required in signal and image processing. In this paper, we propose an array processor utilizing an effective data I/O mechanism featuring external FIFOs. The FIFOs are used to buffer initial matrix data and partially processed results. Therefore, if all required data are stored in the FIFOs, matrix operations, including the algorithm to solve the Algebraic Path Problem (APP), can be performed without any data I/Os. In addition, we can eliminate register files from the processing elements (PEs) if we construct the PE array by controlling the external FIFOs systematically and transferring the data from (to) the FIFOs to (from) the PE array. This enables us to simplify each PE structure and realize a large array processor with limited hardware resources. Here, the FIFOs themselves can be easily realized using conventional discrete FIFO or memory chips.
Starting Page	255
Ending Page	260
File Size	399585
Page Count	6
File Format	PDF
ISBN	9781424423576
DOI	10.1109/CIT.2008.4594683
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-08
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Radiation detectors Computer architecture Three dimensional displays Registers Arrays Indexes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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