NDLI: FPGA Realization of Activation Function for Artificial Neural Networks

Content Provider	IEEE Xplore Digital Library
Author	Saichand, V. Nirmala, D.M. Arumugam, S. Mohankumar, N.
Copyright Year	2008
Description	Author affiliation: Nanda Coll. of Eng. (Arumugam, S.) \|\| Sch. of Eng., Amrita Vishwa Vidyapeetham (Saichand, V.; Nirmala, D.M.; Mohankumar, N.)
Abstract	Implementation of artificial neural network (ANN) in hardware is needed to fully utilize the inherent parallelism. Presented work focuses on the configuration of field-programmable gate array (FPGA) to realize the activation function utilized in ANN. The computation of a nonlinear activation function (AF) is one of the factors that constraint the area or the computation time. The most popular AF is the log-sigmoid function, which has different possibilities of realizing in digital hardware. Equation approximation, lookup table (LUT) based approach and piecewise linear approximation (PWL) are a few to mention. A two-fold approach to optimize the resource requirement is presented here. Primarily, fixed-point computation (FXP) that needs minimal hardware, as against floating-point computation (FLP) is followed. Secondly, the PWL approximation of AF with more precision is proved to consume lesser Si area when compared to LUT based AF. Experimental results are presented for computation.
Starting Page	159
Ending Page	164
File Size	156692
Page Count	6
File Format	PDF
ISBN	9780769533827
DOI	10.1109/ISDA.2008.333
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-26
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	ANN Lookup table based Neurons Piecewise linear approximation FPGA Artificial neural networks Very large scale integration Table lookup Function approximation Design engineering Activation Function Parallel processing Piecewise Linear Approximation Hardware Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

FPGA Implementation of Artificial Neurons: Comparison study

Computation of a nonlinear squashing function in digital neural networks

Implementation framework for Artificial Neural Networks on FPGA

Approximation of hyperbolic tangent activation function using hybrid methods

Artificial neural networks activation function HDL coder

A non-linear approximation of the sigmoid function based on FPGA

A mixed parallel neural networks computing unit implemented in FPGA

FPGA implementation of an ANN for detection of anthelmintics resistant nematodes in sheep flocks

High precision FPGA implementation of neural network activation functions

FPGA Realization of Activation Function for Artificial Neural Networks

Similar Documents

FPGA Implementation of Artificial Neurons: Comparison study

Computation of a nonlinear squashing function in digital neural networks

Implementation framework for Artificial Neural Networks on FPGA

Approximation of hyperbolic tangent activation function using hybrid methods

Artificial neural networks activation function HDL coder

A non-linear approximation of the sigmoid function based on FPGA

A mixed parallel neural networks computing unit implemented in FPGA

FPGA implementation of an ANN for detection of anthelmintics resistant nematodes in sheep flocks

High precision FPGA implementation of neural network activation functions

FPGA Realization of Activation Function for Artificial Neural Networks