NDLI: Dynamic Flash-memory Allocation for Smartcards: how to cope with limited space (in a short life)

Content Provider	IEEE Xplore Digital Library
Author	Aendenroomer, A.J.R. Huang, S.
Copyright Year	2007
Description	Author affiliation: Singapore Inst. of Manuf. Technol. (SIMTech), Singapore (Aendenroomer, A.J.R.; Huang, S.)
Abstract	Fully flash-memory based smartcards provide and constrain us with the scope of this paper and the objectives of the research presented here are: how to deal with tackling the two issues related to smartcards based on flash-memory. The first issue deals with the limited amount of memory on a smartcard: the (low-end / mass-market) smartcards this research deals with are in the range of 16 to 64 kByte of allocatable memory, that is for application, operating system and data altogether. The second issue deals with the physical properties of flash-memory, which directly translates in the number of erase cycles: typically in the order of 10,000 to 100,000. This paper presents research results, conducted towards tackling these two issues into a viable solution for mass-market applications. Because the application is meant for smartcards, the constraints imposed on the scope can be stated as: try to save on silicon wherever possible, while minimizing the chance that the maximum number of erase cycles will be reached within the lifespan of the card (which is typically in the range of 2-3 years). The solution proposed by our research mainly combines best-practices from many years of dynamic memory allocation research and applications in general as well as novel bit-level management policies. These bit-level policies are imposed on the allocation mechanism, which is based on utilizing "loose" bits that are squeezed out after ASCII encoding and other encoding and allocation policies that can do with less-than-eight-bit bytes. It is shown in this paper that the information that can be captured into those "loose" bits is sufficient to manage the erasure policy over the different memory blocks. Implementing this policy requires some coding in the operating system; however implementing the policy will decrease the likelihood that the maximum number of erasure cycles will be reached within the expected lifetime of the smartcard's deployment in mass-market applications.
Starting Page	835
Ending Page	840
File Size	947948
Page Count	6
File Format	PDF
ISBN	9781424408504
ISSN	19354576
DOI	10.1109/INDIN.2007.4384882
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-23
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Operating systems Memory management Flash memory Data compression Read-write memory Silicon Encoding Time factors Compression algorithms
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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