NDLI: Design and evaluation of a media-oriented vector processor with a multi-banked cache memory

Content Provider	IEEE Xplore Digital Library
Author	Ye Gao Shoji, N. Egawa, R. Takizawa, H. Kobayashi, H.
Copyright Year	2013
Description	Author affiliation: Cyberscience Center, Tohoku Univ., Sendai, Japan (Egawa, R.; Kobayashi, H.) \|\| Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan (Ye Gao; Shoji, N.; Takizawa, H.)
Abstract	Vector processors have significant advantages for next generation multimedia applications (MMAs). One of them is that vector processors can achieve a high data transfer performance and thus a high computing performance by using a high bandwidth memory sub-system. However, their high bandwidth memory sub-systems usually lead to enormous costs in terms of chip area, power consumption and energy consumption. These costs are too expensive for an embedded computer system, which is the main execution platform of MMAs. In order to enable an embedded computer system to exploit the high memory bandwidth and thus the high performance of the vector architecture, this paper proposes a media-oriented vector processor (MVP) with a multi-banked cache memory (MVP-cache). Different from conventional multi-banked cache memories, MVP-cache makes multiple independent data arrays of small size cache lines share one tag array. In this way, MVP-cache can consume less static power consumption on its tag arrays because of the reduction in the tag array size. MVP-cache can also achieve a high efficiency on short vector data transfers because the flexibility of data transfers can be improved by independently controlling the data transfers of each data array. Moreover, in order to fully exploit the bandwidth of MVP-cache, MVP also introduces an out-of-order vector processing mechanism. By using these mechanisms, MVP expands the potential of vector architectures on media processing in embedded computer systems.
Starting Page	78
Ending Page	87
File Size	577977
Page Count	10
File Format	PDF
ISBN	9781479912841
DOI	10.1109/ESTIMedia.2013.6704506
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-03
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cache memory Pipelines Bandwidth Data transfer Vectors Registers Arrays
Content Type	Text
Resource Type	Article

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