NDLI: Efficient Reed-Solomon decoder with adaptive error-correcting capability

Content Provider	IEEE Xplore Digital Library
Author	Jiangli Zhu Xinmiao Zhang
Copyright Year	2010
Description	Author affiliation: Case Western Reserve University, USA (Jiangli Zhu; Xinmiao Zhang)
Abstract	Reed-Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. This paper proposes an efficient architecture for RS decoder with adaptive error-correcting capability. This decoder can be employed to enable complexity-performance tradeoff and ensure data reliability in applications with time-varying channel condition, such as wireless communications. Specifically, the proposed decoder adopts the low-complexity Chase (LCC) algebraic soft-decision decoding algorithm. This algorithm tests 2η vectors, and larger η leads to higher error-correcting capability. The proposed decoder is capable of implementing LCC decoding with variable η. In addition, the decoder hardware units are reused to incorporate hard-decision decoding (HDD). Detailed hardware requirement and latency analysis is provided for a (255, 239) RS code. Compared to the LCC decoder for η = 3 only, the adaptive RS decoder that can take care of both the HDD and LCC decoding with η ∈ {3, 4, 5} only has 1% area overhead.
Starting Page	1
Ending Page	4
File Size	373515
Page Count	4
File Format	PDF
ISBN	9781424475971
e-ISBN	9781424475964
DOI	10.1109/WOCC.2010.5510637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-14
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low-complexity Chase VLSI design Decoding Delay Reed-Solomon codes Interpolation Adaptive error-correcting capability Algebraic soft-decision decoding Variable speed drives Time-varying channels Digital communication Hardware Polynomials Hard-decision decoding Testing
Content Type	Text
Resource Type	Article

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