NDLI: A High Speed Interleaver for Emerging Wireless Communications

Content Provider	IEEE Xplore Digital Library
Author	Yuan-Wei Wu Pangan Ting Hsi-Pin Ma
Copyright Year	2005
Description	Author affiliation: Comput. & Commun. Lab., Ind. Technol. Res. Inst., Hsinchu (Yuan-Wei Wu; Pangan Ting)
Abstract	In this paper, a novel high-speed interleaver/deinterleaver is proposed. As data rates demanded in emerging communication applications increase, architectures for high-speed interleaving become essential. Three pipelined blocks comprise the interleaver to execute three permutation steps in high speed. The addition of static random access memories (SRAM) in stage 1 speeds up 24 times of interleaving efficiency. Operating at 200 MHz, this design accomplishes the overall throughput of 4.8 Gbps. The memory architecture of this interleaver can be configured to dynamically enable and disable memory blocks for low power consumption. This flexible design can perform both interleaving and deinterleaving functions. It supports different wireless standards as well, such as IEEE standard (Std.) 802.16a, IEEE Std. 802.11a/g, and IEEE 802.11 in proposal
Starting Page	1192
Ending Page	1197
File Size	2822360
Page Count	6
File Format	PDF
ISBN	0780393058
DOI	10.1109/WIRLES.2005.1549581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wireless communication Convolutional codes Random access memory Computer architecture Interleaved codes Turbo codes MIMO Decoding Proposals Application software
Content Type	Text
Resource Type	Article

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