NDLI: Fault Models of CMOS Gates: An Empirical Study Based on Mutation Analysis

Content Provider	IEEE Xplore Digital Library
Author	Xiaofeng Tang Aiqiang Xu Wenhai Li Zhiyong Yang
Copyright Year	2014
Description	Author affiliation: Dept. of Sci. Res., Naval Aeronaut. & Astronaut. Univ., Yantai, China (Xiaofeng Tang; Aiqiang Xu; Wenhai Li; Zhiyong Yang)
Abstract	An empirical study is conducted to analyze the fault models of CMOS gates in VLSI. The mutation analysis methodology is used to ensure the simulation experiments are sufficient enough. For the primitive CMOS logic cells: inverter, 2-input NAND, NOR and XOR gates, a total of 335 mutant circuits are generated, simulated and analyzed. Comparing with the previous work, several new fault models are revealed, such as other-logic and the indetermination fault categorys sub-categories: 0-to-X, 1-to-X and other-to-X. Besides, the experimental results show that the classic static stuck-at fault cannot cover many practical defects in a circuit since it just averagely accounts for less than 15% of the total faults. Many other useful conclusions are drawn, which may benefit the related fault-based applications.
Sponsorship	IEEE Comput. Soc.
Starting Page	115
Ending Page	120
File Size	360510
Page Count	6
File Format	PDF
e-ISBN	9781479950799
DOI	10.1109/DASC.2014.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-24
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Analytical models fault model VLSI mutation analysis Logic gates CMOS gate CMOS integrated circuits Circuit faults Transistors Integrated circuit modeling
Content Type	Text
Resource Type	Article

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