NDLI: Load-Aware Dynamic Partial Reconfiguration Implementation of Crossbar Scheduler

Content Provider	IEEE Xplore Digital Library
Author	Shaobin Zhang Tongsen Hu Minghui Wu Tianzhou Chen Zening Qu
Copyright Year	2011
Abstract	FPGA dynamic partial reconfiguration (DPR) tend to be adopted for its flexibility and fewer resource consumption increasingly in hardware implementation, especially in communication devices. A crossbar scheduling algorithm is used to schedule the crossbar, or decide the order in which cells will be served. The is lip and FIRM are two classic crossbar scheduling algorithms, but they do not support DPR. Performance of these two algorithms differs under varying workloads (load: cells' arrival speed). With the development of DPR, implementations of these algorithms will have improvement both in performance and resource usage. DPR reduces 7.249% average delay than iSlip does and 0.013% average delay than FIRM does in 4x4 crossbar. It reduces 17.9% average delay than iSlip does and 0.039% average delay than FIRM does in 8x8 crossbar. In this paper, we compared the DPR implementation and non-DPR implementations (iSlip and FIRM) and found that the former reduces 37.744% LUTs and 47.874% FFs in 4x4 crossbar, and 47.325% LUTs and 49.907% FFs in 8x8 crossbar.
Starting Page	252
Ending Page	258
File Size	466124
Page Count	7
File Format	PDF
ISBN	9781467300063
DOI	10.1109/DASC.2011.62
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-12
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Schedules dynamic partial reconfiguration FPGA Switches Educational institutions Scheduling crossbar Delay Scheduling algorithm
Content Type	Text
Resource Type	Article

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