NDLI: A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag

Content Provider	IEEE Xplore Digital Library
Author	Qiasi Luo Li Guo Qing Li Gang Zhang Junyu Wang
Copyright Year	2009
Description	Author affiliation: State Key Lab of ASIC & System, School of Microelectronics, Fudan University, Shanghai, 201203, China (Qing Li; Gang Zhang; Junyu Wang) \|\| Department of Electronic Science and Technology, University of Science and Technology of China, Hefei, 230026, China (Qiasi Luo; Li Guo)
Abstract	Power consumption is critical to the performance of EPC Gen2 RFID tags. System clock frequency of tags should be as low as possible to reduce the power consumption and still conform to the protocol. This paper analyses the impact of different clock strategies on digital circuits of EPC Gen2 tag. An error shift approach is proposed to reduce the backscatter link frequency (BLF) errors. A dual-clock strategy with both 1.28 and 2.56 MHz clocks for the digital circuits is developed. Compared with the 1.92 MHz unitary-clock strategy, the dual-clock strategy offers larger decoding margins and BLF margins, consumes 5.66% to 9.44% less power estimated in CMOS 0.18μm technologies, and fully conforms to the EPC Gen2 protocol as well.
Starting Page	7
Ending Page	14
File Size	657403
Page Count	8
File Format	PDF
ISBN	9781424433377
DOI	10.1109/RFID.2009.4911177
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Protocols RFID Encoding Decoding RFID tags Digital circuits protocol conformance backscatter frequency clock strategy EPC Gen2 Frequency Clocks Radiofrequency identification Backscatter
Content Type	Text
Resource Type	Article

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