NDLI: Test Patterns for Verilog Design Error Localization

Content Provider	IEEE Xplore Digital Library
Author	Peischl, B. Riaz, N. Wotawa, F.
Copyright Year	2009
Abstract	In this article we briefly state the idea behind modelbased diagnosis and its application to debugging RTL (Register Transfer Level) Verilog designs. In providing a debugging model for the Verilog HDL (Hardware Description Language) we rely on a specific abstraction (trace semantics) that captures solely quiescent states of the design. In this vein we manage to overcome the inherent complexity issues of event-based Verilog without relying on specific fault models. To leverage test patterns for design error localization we propose the filtering approach and relate it to the concept of Ackermann constraints. Notably, our empirical results demonstrate that our novel technique considerably increases the diagnosis resolution even under presence of only a couple of test cases. The article outlines a case study comprising several circuits, where the proposed technique allowed one for excluding 95 per cent of the Verilog code from being faulty by merely considering a couple of test cases.
Starting Page	111
Ending Page	120
File Size	325533
Page Count	10
File Format	PDF
ISBN	9780769538204
DOI	10.1109/TAICPART.2009.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-04
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software testing Fault diagnosis Filtering Object oriented modeling Circuit faults Application software Hardware design languages Software debugging Circuit testing Software engineering
Content Type	Text
Resource Type	Article

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