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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Zhe Liu Hao Che Kai Zheng Shanzhen Chen Bin Liu |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., Tsinghua Univ., Beijing, China (Zhe Liu) |
| Abstract | Network processor (NP) is a new breed of packet forwarding engine that is designed to meet the simultaneous demands of high speed and great flexibility of today's network equipments. Cache mechanism has attracted more and more attentions in the field of NP design because of its big success in terms of latency hiding. In this paper, we evaluate the effectiveness of cache mechanism for NP under the new context of packet forwarding using real-life packet traces. Our results suggest that caching can reduce the packet loss rate to an extremely low level under reasonable hit rate and packet buffer size. However, the possibility of incurring large queuing delay makes it unsuitable for applications demanding stringent quality of service (QoS) enforcement. Furthermore, we also show that the combination of cache mechanism with multithreading will be a promising way because of the dramatically decreased both queuing and processing delay, in addition to the even lower packet loss rate. |
| Starting Page | 978 |
| Ending Page | 981 |
| File Size | 272215 |
| Page Count | 4 |
| File Format | |
| ISBN | 078039335X |
| DOI | 10.1109/WCNM.2005.1544215 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-09-26 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Associative memory Multithreading Processor scheduling Prefetching Random access memory Quality of service Access protocols Added delay Engines Coprocessors |
| Content Type | Text |
| Resource Type | Article |
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