NDLI: Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication

Content Provider	IEEE Xplore Digital Library
Author	Guo Li Wang Miao-feng Qiu Tian Liu Lu Luo Feng
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei (Guo Li; Wang Miao-feng; Qiu Tian; Liu Lu; Luo Feng)
Abstract	Based on Horner' rule and Baugh-Wooley algorithm, this paper presents two novel bit-level parallel array algorithms of 2's complement multiplication, and the algorithms have been mapped to systolic arrays by using linear mapping techniques. We propose two efficient systolic arrays of multiply and accumulate (MAC) operation and we also describe the vector-vector and matrix-matrix multiplication that can be efficiently implemented by using the MAC arrays. The two systolic arrays have high performance (low time complexity, space complexity and latency) and consume smaller gate-area in comparison to other architectures. It is suitable for VLSI implementation for its regularity and modularity
Sponsorship	IEEE Circuits and Syst. Soc. HKUST UESTC City Univ. of Hong Kong
Starting Page	567
Ending Page	570
File Size	3314386
Page Count	4
File Format	PDF
ISBN	0780395840
DOI	10.1109/ICCCAS.2006.284700
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-25
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital systems Very large scale integration Systolic arrays Mathematical model Speech processing Kernel Delay Arithmetic
Content Type	Text
Resource Type	Article

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