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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Liang-Hwa Chen Po-Lun Chang Yen-Ching Chang Chiou-Yng Lee |
| Copyright Year | 2012 |
| Abstract | A novel low-complexity scalable architecture for dual basis multiplications over GF(2m) is proposed in this paper. This multiplier architecture is derived from the Hankel matrix-vector representation of dual basis multiplication, and is feasible for the finite fields generated by irreducible trinomials. By appropriately selecting its digit size, the proposed scalable architecture can achieve a satisfactory trade-off between hardware complexity and throughput performance for implementing ECC cryptosystems such as ECDSA in resource-constrained environments such as embedded systems and smart cards. Analytical results exhibit that the space complexity of the proposed multiplier architecture is substantially lower than that of the non-scalable architectures. Besides, owing to its features of regularity, modularity and concurrency, the proposed architecture is highly feasible for VLSI implementations. |
| Starting Page | 45 |
| Ending Page | 50 |
| File Size | 206084 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467309172 |
| DOI | 10.1109/ISBAST.2012.13 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-03-26 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Finite field Latches Dual basis Hankel matrix-vector Computer architecture Elliptic curve cryptography (ECC) Logic gates Scalable multiplier Vectors Registers Complexity theory Cryptography |
| Content Type | Text |
| Resource Type | Article |
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