NDLI: Architecture-level fault-tolerance for biomedical implants

Content Provider	IEEE Xplore Digital Library
Author	Seepers, R.M. Strydis, C. Gaydadjiev, G.N.
Copyright Year	2012
Description	Author affiliation: Dept. of Neuroscience, Erasmus MC, Dr. Molewaterplein 50, 3015 GE Rotterdam, The Netherlands (Seepers, R.M.; Strydis, C.) \|\| Department of Computer Science and Engineering, Chalmers University of Technology, Rannvagen 6, Goteburg, Sweden (Gaydadjiev, G.N.)
Abstract	In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants. The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance techniques. The proposed architecture allows run-time tradeoffs between performance and fault tolerance by means of instruction-level configurability. The system design is synthesized for UMC 90nm CMOS standard-process and is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that area and power overheads of approximately 25% and 32%, respectively, are required to implement our techniques on the baseline processor. The major overheads of the proposed architecture are performance (up to 107%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is targeted. It is shown that test sequences can effectively be scheduled during the available program stalls and that nearly all soft faults are tolerated by using instruction duplication. The main advantages of the proposed architecture are the high portability of the introduced architecture-level fault-tolerance techniques, the flexibility in trading processor overheads for required fault-tolerance degree as well as affordable area and power consumption overheads.
Starting Page	104
Ending Page	112
File Size	1218829
Page Count	9
File Format	PDF
ISBN	9781467322959
e-ISBN	9781467322973
e-ISBN	9781467322966
DOI	10.1109/SAMOS.2012.6404163
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-16
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Runtime Fault tolerant systems Computer architecture Hardware Registers Circuit faults
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Roadmap for Autonomous Fault-Tolerant Systems

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

An effective hybrid fault-tolerant architecture for pipelined cores

Datapath fault tolerance for parallel accelerators

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs

Design and architectures for dependable embedded systems

Error recovery technique for coarse-grained reconfigurable architectures

Analyzing fault effects in fault insertion experiments

Bit-Flipping Scan — A unified architecture for fault tolerance and offline test

Architecture-level fault-tolerance for biomedical implants

Similar Documents

A Roadmap for Autonomous Fault-Tolerant Systems

Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

An effective hybrid fault-tolerant architecture for pipelined cores

Datapath fault tolerance for parallel accelerators

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs

Design and architectures for dependable embedded systems

Error recovery technique for coarse-grained reconfigurable architectures

Analyzing fault effects in fault insertion experiments

Bit-Flipping Scan — A unified architecture for fault tolerance and offline test

Architecture-level fault-tolerance for biomedical implants