NDLI: Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems

Content Provider	IEEE Xplore Digital Library
Author	Tumeo, A. Pilato, C. Ferrandi, F. Sciuto, D. Lanzi, P.L.
Copyright Year	2008
Description	Author affiliation: Dipt. di Elettron. e Inf., Politec. di Milano, Milan (Tumeo, A.; Pilato, C.; Ferrandi, F.; Sciuto, D.; Lanzi, P.L.)
Abstract	Heterogeneous multiprocessor systems, assembled with off-the-shelf processors and augmented with reprogrammable devices, thanks to their performance, cost effectiveness and flexibility, have become a standard platform for embedded systems. To fully exploit the computational power offered by these systems, great care should be taken when deciding on which processing element (mapping) and when (scheduling) executing the program tasks. Unfortunately, both these problems are NP-complete, and, even if they are strictly interconnected, they are normally performed separately with exact or heuristic algorithms to simplify the search for the optimum points. In this paper we present an exploration algorithm based on Ant Colony Optimization (ACO) that tries to solve the two problems simultaneously. We propose an implementation of the algorithm that gradually constructs feasible solution instances and searches around them rather than exploring a structure that already considers all the possible solutions. We introduce a two-stage decision mechanism that simplifies the data structures but lets the ant perform correlated choices for both the mapping and the scheduling. We show that this algorithm provides better and more robust solutions in less time than the Simulated Annealing and the Tabu Search algorithms, extended to support the combined scheduling and mapping problems. In particular, our ACO formulation can find, on average, solutions between 64% and 55% better than Simulated Annealing and Tabu Search.
Starting Page	142
Ending Page	149
File Size	722398
Page Count	8
File Format	PDF
ISBN	9781424419852
DOI	10.1109/ICSAMOS.2008.4664857
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-21
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ant colony optimization Assembly systems Costs Processor scheduling Heuristic algorithms Embedded system Power system interconnection Simulated annealing Scheduling algorithm Multiprocessing systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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