NDLI: A hybrid current-mode passive second-order continuous-time ΣΔ modulator

Content Provider	IEEE Xplore Digital Library
Author	Sniatala, P. Naumowicz, M. de Melo, J.L.A. Paulino, N. Goes, J.
Copyright Year	2014
Description	Author affiliation: Dept. de Eng. Electrotec., Univ. Nova de Lisboa, Caparica, Portugal (de Melo, J.L.A.; Paulino, N.; Goes, J.) \|\| Dept. of Comput. Eng., Poznan Univ. of Technol., Poznan, Poland (Sniatala, P.; Naumowicz, M.)
Abstract	This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.
Starting Page	117
Ending Page	120
File Size	658596
Page Count	4
File Format	PDF
e-ISBN	9788363578053
DOI	10.1109/MIXDES.2014.6872168
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-19
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Department of Microelectronics and Computer Science
Subject Keyword	Sigma-delta modulation Current-Mode Frequency modulation Power demand Sigma-Delta Modulator CMOS integrated circuits Mirrors Clocks
Content Type	Text
Resource Type	Article

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