NDLI: Achieving up to zero communication delay in BSP-based graph processing via vertex categorization

Content Provider	IEEE Xplore Digital Library
Author	Xuhong Zhang Ruijun Wang Xunchao Chen Jun Wang Lukasiewicz, T. Dezhi Han
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA (Xuhong Zhang; Ruijun Wang; Xunchao Chen; Jun Wang; Lukasiewicz, T.) \|\| Coll. of Inf. Eng., Shanghai Maritime Univ., Shanghai, China (Dezhi Han)
Abstract	The Bulk Synchronous Parallel (BSP) model, which divides a graphing algorithm into multiple supersteps, has become extremely popular in distributed graph processing systems. However, the high number of network messages exchanged in each superstep of the graph algorithm will create a long period of time. We refer to this as a communication delay. Furthermore, the BSP's global synchronization barrier does not allow computation in the next superstrep to be scheduled during this communication delay. This communication delay makes up a large percentage of the overall processing time of a superstep. While most recent research has focused on reducing number of network messages, but communication delay is still a deterministic factor for overall performance. In this paper, we add a runtime communication and computation scheduler into current graph BSP implementations. This scheduler will move some computation from the next superstep to the communication phase in the current superstep to mitigate the communication delay. Finally, we prototyped our system, Zebra, on Apache Hama, which is an open source clone of the classic Google Pregel. By running a set of graph algorithms on an in-house cluster, our evaluation shows that our system could completely eliminate the communication delay in the best case and can achieve average 2X speedup over Hama.
Starting Page	112
Ending Page	121
File Size	833942
Page Count	10
File Format	PDF
e-ISBN	9781467378918
DOI	10.1109/NAS.2015.7255213
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Roads Clustering algorithms Delays Partitioning algorithms Synchronization Message systems
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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