NDLI: A Processor-DMA-Based Memory Copy Hardware Accelerator

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2015 IEEE International Conference on Networking, Architecture and Storage (NAS)

2014 9th IEEE International Conference on Networking, Architecture, and Storage

2013 IEEE Eighth International Conference on Networking, Architecture and Storage

2012 IEEE Seventh International Conference on Networking, Architecture, and Storage

2011 IEEE Sixth International Conference on Networking, Architecture, and Storage

Table of Contents

Conference Committees

Program Committee Members

ThinStore: Out-of-Band Virtualization with Thin Provisioning

Adaptive Virtual Machine Provisioning in Elastic Multi-tier Cloud Platforms

Hybrid Co-scheduling Optimizations for Concurrent Applications in Virtualized Environments

Transition from IPv4 to IPv6: A Translation Approach

Applying Modified TAM to Privacy Setting Tools on SNS

Using Entropy to Classify Traffic More Deeply

Request Load Balancing for Highly Skewed Traffic in P2P Networks

A Probabilistic Acknowledgment Mechanism for Wireless Sensor Networks

A Preventive Traffic Adaptation Model for Wireless Mesh Networks Using Fuzzy Logic

Data Allocation in Heterogeneous Disk Arrays

Performance, Reliability, and Performability Aspects of Hierarchical RAID

A Comprehensive Study on RAID-6 Codes: Horizontal vs. Vertical

PDRS: A New Recovery Scheme Application for Vertical RAID-6 Code

JVM Virtual Method Invoking Optimization Based on CAM Table

Towards Scalable Application Checkpointing with Parallel File System Delegation

TMTLS: Combine TM with TLS to Limit the Memory Contentions and Exploit the Parallelism in the Long-Running Transactions

Performance and Power Analysis of ATI GPU: A Statistical Approach

Exploring the Difference of Power-Aware Cluster Schedulers

Research on Energy Consumption of General Network Storage System

Secure Fragment Allocation in a Distributed Storage System with Heterogeneous Vulnerabilities

Low Bitrate Asynchronous Replication of Block Devices and Virtual Machines

Resource Discovery in Large Scale Network Infrastructure

An Integrated System Solution for Secure P2P Content Distribution Based on Network Coding

Understanding Long-Term Evolution and Lifespan in Peer-to-Peer Systems

Feedback Based Sparse Recovery for Motion Tracking in RF Sensor Networks

Traffic-Aware Spectrum Assignment in Wireless Networks

A Point-to-Multipoint Distribution Mechanism for IPTV Video Network

Error Detection by Redundant Transaction in Transactional Memory System

A Processor-DMA-Based Memory Copy Hardware Accelerator

Performance Improvement for Multicore Processors Using Variable Page Technologies

Processes Scheduling on Heterogeneous Multi-core Architecture with Hardware Support

A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding

EMFS: Email-based Personal Cloud Storage

Using Eager Strategies to Improve NFS I/O Performance

QMDS: A File System Metadata Management Service Supporting a Graph Data Model-Based Query Language

Efficient, Modular Metadata Management with Loris

An Efficient Shared Memory Based Virtual Communication System for Embedded SMP Cluster

Coherent Temporal Streams in PARSEC

Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs

Azor: Using Two-Level Block Selection to Improve SSD-Based I/O Caches

Classified Power Capping with Distribution Trees in Cloud Computing

Energy Efficient Buffer Cache Replacement for Data Servers

Evaluating Energy and Performance for Server-Class Hardware Configurations

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle

EthSpeeder: A High-performance Scalable Fault-Tolerant Ethernet Network Architecture for Data Center

HR-NET: A Highly Reliable Message-Passing Mechanism for Cluster File System

Scalable Index Update for Block-Level Continuous Data Protection

Detecting Duplicates over Sliding Windows with RAM-Efficient Detached Counting Bloom Filter Arrays

Publisher Information

2010 IEEE Fifth International Conference on Networking, Architecture, and Storage

2009 IEEE International Conference on Networking, Architecture, and Storage

2008 International Conference on Networking, Architecture, and Storage

2007 International Conference on Networking, Architecture, and Storage (NAS 2007)

A Processor-DMA-Based Memory Copy Hardware Accelerator

Content Provider	IEEE Xplore Digital Library
Author	Wen Su Ling Wang Menghao Su Su Liu
Copyright Year	2011
Abstract	For many Operating Systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage of a proposed Direct Memory Access (DMA) engine in the processor which overcomes many conventional DMA engine shortcomings. Experimental results show that the proposed hardware solution achieves a speedup of 14.79 compared with the optimized software solution and an overlap of 81.8% in computing and data transfer on average.
Starting Page	225
Ending Page	229
File Size	168246
Page Count	5
File Format	PDF
ISBN	9781457711725
e-ISBN	9780769545097
DOI	10.1109/NAS.2011.15
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	accelerator memory copy Computer architecture Bandwidth DMA Hardware Software Central Processing Unit Acceleration processor Engines
Content Type	Text
Resource Type	Article

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