NDLI: TS-LDPC analog decoding based on the Min-Sum algorithm

Content Provider	IEEE Xplore Digital Library
Author	Abolfazli, A.R. Shayan, Y.R. Cowan, G.E.R.
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Computer Engineering, Concordia University, Montreal, Quebec (Abolfazli, A.R.; Shayan, Y.R.; Cowan, G.E.R.)
Abstract	It has been shown that Min-Sum (MS) algorithms have low complexity in the implementation of analog VLSI decoders compared to the Sum-Product (SP) algorithm. Moreover, Turbo-structured LDPC (TS-LDPC) codes are known to have lower error floor than random LDPC codes. In this paper, Min-Sum and Min-Sum with correction factor algorithms are reviewed and adapted with TS-LDPC codes for future analog VLSI implementation. Simulation results show that the error performance of the Min-Sum algorithm is comparable with the Sum-Product algorithm for the same block length. This means that the lower error floor property of TS-LDPC codes is preserved when MS algorithms are used. Moreover, analog decoder implementation of TS-LDPC codes is studied. To test the suitability of the MS algorithm based TS-LDPC decoder some analog impairments such as mismatch, leakage and noise are considered in the decoding procedure of TS-LDPC codes. In each case, it is shown that the degradation of the error performance of TS-LDPC codes due to analog impairments is negligible. Therefore, it can be concluded that the analog decoder of the TS-LDPC code using MS algorithm is fairly robust against analog imperfections and may be considered in future implementation of analog VLSI decoder.
Starting Page	162
Ending Page	167
File Size	433231
Page Count	6
File Format	PDF
ISBN	9781467311137
e-ISBN	9781467311144
e-ISBN	9781467311120
DOI	10.1109/QBSC.2012.6221374
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-28
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Simulation Very large scale integration Approximation algorithms Decoding Iterative decoding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An improved LDPC decoding algorithm based on min-sum algorithm

An improved normalized min-sum algorithm for LDPC codes

Design of turbo decoder based on Min-Sum decoding algorithm of LDPC code

Min-sum algorithm-structure based decoding algorithms for LDPC codes

Using self-correction for min-sum based decoding algorithms of LDPC codes

A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm

Modified min-sum decoding algorithm for LDPC codes based on classified correction

Optimized Min-Sum decoding algorithm for Low Density PC codes

Performance of Min-Sum for Decoding Fountain Codes over BIAWGN Channels

TS-LDPC analog decoding based on the Min-Sum algorithm

Similar Documents

An improved LDPC decoding algorithm based on min-sum algorithm

An improved normalized min-sum algorithm for LDPC codes

Design of turbo decoder based on Min-Sum decoding algorithm of LDPC code

Min-sum algorithm-structure based decoding algorithms for LDPC codes

Using self-correction for min-sum based decoding algorithms of LDPC codes

A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm

Modified min-sum decoding algorithm for LDPC codes based on classified correction

Optimized Min-Sum decoding algorithm for Low Density PC codes

Performance of Min-Sum for Decoding Fountain Codes over BIAWGN Channels

TS-LDPC analog decoding based on the Min-Sum algorithm