NDLI: "Glitch Logic" and Applications to Computing and Information Security

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2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security

Cover Art

Conference Organizers

Program Committee and Reviewers

Invited Talk 1

Invited Talk 2

Fundamentals of Biometric System Design: New Course for Electrical, Computer, and Software Engineering Students

Fingerprint - Iris Fusion Based Identification System Using a Single Hamming Distance Matcher

Experiments with Fingerprint Image Quality

Color Iris Recognition Using Hypercomplex Gabor Wavelets

Color Iris Recognition Using Quaternion Phase Correlation

Gait Recognition Using Shadow Analysis

Automating the Processes Involved in Facial Composite Production and Identification

Commercial Face Recognition Doesn't Work

Caricaturing to Improve Face Matching

Finding and Discriminating Faces Using Biological Barcodes

Toward a HLAC-Based Histological Diagnosis System for Virtual-Slide Images

Recognition of Dynamic Texture Patterns Using CHLAC Features

Histopathological Diagnostic Support Technology Using Higher-Order Local Autocorrelation Features

Anomalousness Detection for Surgery Videos Using CHLAC Feature

Architecturally-Enforced InfoSec in a General-Purpose Self-Configurable System

Mechatronic Security and Robot Authentication

Autonomous Physical Secret Functions and Clone-Resistant Identification

Characterization of a Voltage Glitch Attack Detector for Secure Devices

Research on Critical Infrastructures and Critical Information Infrastructures

Crossed Crypto-Scheme in WPA PSK Mode

"Glitch Logic" and Applications to Computing and Information Security

Ensuring Secure Healthcare Communications via ICmetric Based Encryption on Unseen Devices

Color Texture Retrieval Using Hypercomplex Wavelets

The Radiation Tolerance Problem: Analytical Modelling of Inter-Dependency of Parameters

A Method of Project Evaluation and Review Technique (PERT) Optimization by Means of Genetic Programming

Author index

Publisher's Information

2008 Bio-inspired, Learning and Intelligent Systems for Security

2007 ECSIS Symposium on Bio-inspired, Learning, and Intelligent Systems for Security (BLISS 2007)

"Glitch Logic" and Applications to Computing and Information Security

Content Provider	IEEE Xplore Digital Library
Author	Stoica, A. Katkoori, S.
Copyright Year	2009
Abstract	This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable “glitch logic” processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
Starting Page	107
Ending Page	112
File Size	327726
Page Count	6
File Format	PDF
ISBN	9780769537542
DOI	10.1109/BLISS.2009.1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-20
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	anti-tamper protection to reverse engineering information exfiltration Digital systems Reverse engineering Process control Logic design stego-design Delay Digital circuits Logic circuits trusted design Information security Computer applications Information processing hardware vulnerabilities
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Using logic-based reduction for adversarial component recovery

Circuit camouflage integration for hardware IP protection

Dynamic Polymorphic Reconfiguration for anti-tamper circuits

Circuit Camouflage Integration for Hardware IP Protection

Reverse Engineering Digital Circuits Using Structural and Functional Analyses

A case for tamper-resistant and tamper-evident computer systems.

The Design of Information Flow Control in the Trust Domain Based on the Trusted Terminal

A design verification method for programmable controller software

Security as a new dimension in embedded system design

"Glitch Logic" and Applications to Computing and Information Security

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Using logic-based reduction for adversarial component recovery

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Dynamic Polymorphic Reconfiguration for anti-tamper circuits

Circuit Camouflage Integration for Hardware IP Protection

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A case for tamper-resistant and tamper-evident computer systems.

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"Glitch Logic" and Applications to Computing and Information Security