NDLI: Formal Fault Tolerant Architecture

Content Provider	IEEE Xplore Digital Library
Author	Aljer, A. Devienne, P.
Copyright Year	2010
Abstract	This paper shows the need of development by refinement: from most abstract specification to the implementation, in order to ensure 1) the traceability of the needs and requirements, 2) a good management of the development and 3) a reliable and fault-tolerant design of systems. We propose a formal architecture of models and methods for critical requirements and fault-tolerance. System complexity increases and the choices of their implementation are numerous. So the architecture verification achieves a prominent role in the system design cycle. Fault detecting at this early level decreases the time and costs of correction. We show how a formal method, B method, may be used to write the abstract specification of a system then to product correct-by-construction architecture through many steps of formal refinement. During these steps, a fault scenario is injected with a suitable introspective reaction by the system. All refinement steps, including the introspective correction, should be proven to be correct and satisfy the initial specification of the system. At the lower levels, design is separated between hardware and software communities. But even at these levels many design traces could be captured to prove not only the consistency of each design unit but the coherence between the different sub-parts: software, digital or other technologies
Starting Page	73
Ending Page	78
File Size	386803
Page Count	6
File Format	PDF
ISBN	9781424472734
e-ISBN	9781424472741
DOI	10.1109/CTRQ.2010.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-13
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analysis and Verification Quality of service Reliability theory Conference management Hardware-Software co-design Circuit faults Logic testing Digital circuits Fault tolerance Fault detection Fault tolerant systems Hardware Formal methods
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Fault tolerant digital system design

Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic

A methodology for validating digital circuits with mutation testing

Testing of fault-tolerant hardware through partial control of inputs

Improving fault tolerance utilizing hardware-software-co-synthesis

Solutions to the minimization problem of fault-tolerant logic circuits

Transient fault tolerance in digital systems

Computing bounds for fault tolerance using formal techniques

Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults

Formal Fault Tolerant Architecture

Similar Documents

Fault tolerant digital system design

Formal verification of fail-safeness of a comparator for redundant system using regular temporal logic

A methodology for validating digital circuits with mutation testing

Testing of fault-tolerant hardware through partial control of inputs

Improving fault tolerance utilizing hardware-software-co-synthesis

Solutions to the minimization problem of fault-tolerant logic circuits

Transient fault tolerance in digital systems

Computing bounds for fault tolerance using formal techniques

Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults

Formal Fault Tolerant Architecture