NDLI: Efficient fast transform processor with cost-effective hardware sharing architecture for multi-standard video encoding

Content Provider	IEEE Xplore Digital Library
Author	Chia-Wei Chang Shun-Ji Hsu Chih-Peng Fan
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering, National Chung Hsing University Tai-chung, Taiwan, R.O.C. (Chia-Wei Chang; Shun-Ji Hsu; Chih-Peng Fan)
Abstract	In this paper, fast multiple forward transform algorithms and their hardware sharing designs for 2×2, 4×4, and 8×8 forward transforms in H.264/AVC, and the 8×8 forward transform in AVS, 4×4 and 8×8 forward transforms in VC-1, and DCT in JPEG, MPEG-1/2/4 are developed with a cost effective hardware for the multi-standard video encoding applications. By only shift-and-addition computations, the proposed 1-D hardware sharing transform scheme requires 16.5K gates and is achieved without multiplications. The proposed 1-D sharing architecture reduces the numbers of shifters and adders by up to 36% and 49% respectively, compared with the individual and separate fast algorithm schemes. By VLSI implementations, the 2-D transform processor with the proposed 1-D sharing architecture achieves multi-standard real-time 1080HD video encoding.
Starting Page	14
Ending Page	18
File Size	359632
Page Count	5
File Format	PDF
ISBN	9781467309653
e-ISBN	9781467309646
DOI	10.1109/CISP.2012.6469633
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Video coding Transform coding fast transform Transforms Computer architecture Logic gates hardware share Hardware video coding low cost Standards
Content Type	Text
Resource Type	Article

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