NDLI: Optimization of Memory Allocation for H.264 Video Decoder on Digital Signal Processors

Content Provider	IEEE Xplore Digital Library
Author	Hu, Shuai Zhang, Zhe Zhang, Mengsu Sheng, Tao
Copyright Year	2008
Abstract	The computing power of microprocessors has exponentially increased in the past few decades, so the support to compute intensive multimedia applications has increased too. With such improved computing power, memory subsystem deficiency becomes the major barrier to support video decoder on the Digital Signal Processor (DSP). H.264/AVC becomes the next generation of video codec for embedded systems. In this paper, our focus is to enhance the decoding performance of H.264/AVC through memory optimization for DSP. The experimental results show that the proposed solutions can improve the H.264/AVC decoding speed by almost 37%. Also, the memory optimization method presented in this paper has been integrated into the developed embedded H.264/AVC video decoder. The decoder can perform real time decoding under eight channels of Common Intermediate Format (CIF) frame size, which is the typical requirement of networked video surveillance applications.
Starting Page	71
Ending Page	75
File Size	372345
Page Count	5
File Format	PDF
ISBN	9780769531199
DOI	10.1109/CISP.2008.173
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processors Optimization methods H.264 Multimedia computing Decoding Decoder Video codecs Optimization Microprocessors Embedded system Digital signal processing Computer applications Automatic voltage control
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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