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Content Provider | IEEE Xplore Digital Library |
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Author | Farshidi, E. Alaei-sheini, N. |
Copyright Year | 2009 |
Description | Author affiliation: Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Iran (Farshidi, E.; Alaei-sheini, N.) |
Abstract | In this paper an analog template-based pattern classifier circuit based on a new synthesis of Euclidean distance calculation is presented. It is composed of simple two-quadrant squarer/divider blocks. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (≪20uW), low supply voltage (0.5V), two quadrant input current, wide dynamic range and immunity from body effect. In addition, this classifier circuit is designed in modular methodology, leading to a very regular structure. The circuit was successfully applied to the recognition of some simple patterns. Simulation results by HSPICE show high performance in the separation and classification of circuit. |
Starting Page | 860 |
Ending Page | 863 |
File Size | 496384 |
Page Count | 4 |
File Format | |
ISBN | 9781424444359 |
DOI | 10.1109/SIU.2009.5136532 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-04-09 |
Publisher Place | Turkey |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Low voltage Design methodology Circuit simulation Euclidean distance Dynamic range Circuit synthesis Complexity theory Pattern recognition MOSFETs Immune system |
Content Type | Text |
Resource Type | Article |
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