NDLI: Countering the effects of silicon aging on SRAM PUFs

Content Provider	IEEE Xplore Digital Library
Author	Maes, R. van der Leest, V.
Copyright Year	2014
Description	Author affiliation: Intrinsic-ID, Eindhoven, Netherlands (Maes, R.; van der Leest, V.)
Abstract	Silicon aging, in particular NBTI, causes many PUFs to exhibit a natural tendency of growing less reliable over time. This is inconvenient or even unacceptable for in-the-field applications. In case of SRAM PUFs it is observed that the impact of NBTI aging depends on the data stored in the SRAM. In this work, we investigate the effects of data-dependent silicon aging on SRAM PUF reliability under a number of realistic scenarios. In an accelerated aging experiment on a 65nm CMOS SRAM PUF implementation it is observed that many scenarios cause a smaller reliability reduction than natural aging. Some scenarios even show anti-aging effects, i.e. they cause the SRAM PUF to grow more reliable over time. This is a significant improvement when using an SRAM PUF. Even more so because data-dependent (anti-)aging has a particularly low overhead, requiring neither any changes to the PUF circuit nor any pre-deployment effort.
Starting Page	148
Ending Page	153
File Size	869416
Page Count	6
File Format	PDF
e-ISBN	9781479941124
DOI	10.1109/HST.2014.6855586
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Accelerated aging Random access memory Silicon CMOS integrated circuits Reliability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

Trends in bipolar static random access memory (SRAM) design

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Radiation hardened 256K CMOS SOI SRAM

Pass-transistors pMOS based 8T SRAM cell for layout compaction

Analysis of the reliability impact on high-k metal gate SRAM with assist-circuit

Reliability in VHSIC-level 1.25 mu m radiation-hard CMOS IC devices

Low-power adiabatic SRAM

Countering the effects of silicon aging on SRAM PUFs

Similar Documents

Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS

Investigating the use of an on-chip sensor to monitor NBTI effect in SRAM

Trends in bipolar static random access memory (SRAM) design

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Radiation hardened 256K CMOS SOI SRAM

Pass-transistors pMOS based 8T SRAM cell for layout compaction

Analysis of the reliability impact on high-k metal gate SRAM with assist-circuit

Reliability in VHSIC-level 1.25 mu m radiation-hard CMOS IC devices

Low-power adiabatic SRAM

Countering the effects of silicon aging on SRAM PUFs