NDLI: Robust keys from physical unclonable functions

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2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

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Efficient and secure intellectual property (IP) design with split fabrication

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Side-channel leakage on silicon substrate of CMOS cryptographic chip

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A hierarchical formal approach to verifying side-channel resistant cryptographic processors

Optimality and beyond: The case of 4×4 S-boxes

EM-based detection of hardware trojans on FPGAs

Robust keys from physical unclonable functions

Side-channel countermeasure for SHA-3 at almost-zero area overhead

A frequency leakage model for SCA

Bit selection algorithm suitable for high-volume production of SRAM-PUF

Hardware trojan detection by symmetry breaking in path delays

Experimental evaluation of two software countermeasures against fault attacks

NREPO: Normal basis Recomputing with Permuted Operands

A noise bifurcation architecture for linear additive physical functions

Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter

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New scan attacks against state-of-the-art countermeasures and DFT

Countering the effects of silicon aging on SRAM PUFs

DWM-PUF: A low-overhead, memory-based security primitive

A Chaotic Ring oscillator based Random Number Generator

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2012 IEEE International Symposium on Hardware-Oriented Security and Trust

2011 IEEE International Symposium on Hardware-Oriented Security and Trust

2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2009 IEEE International Workshop on Hardware-Oriented Security and Trust

2008 IEEE International Workshop on Hardware-Oriented Security and Trust

Robust keys from physical unclonable functions

Content Provider	IEEE Xplore Digital Library
Author	Spain, M. Fuller, B. Ingols, K. Cunningham, R.
Copyright Year	2014
Abstract	Weak physical unclonable functions (PUFs) can instantiate read-proof hardware tokens (Tuyls et al. 2006, CHES) where benign variation, such as changing temperature, yields a consistent key, but invasive attempts to learn the key destroy it. Previous approaches evaluate security by measuring how much an invasive attack changes the derived key (Pappu et al. 2002, Science). If some attack insufficiently changes the derived key, an expert must redesign the hardware. An unexplored alternative uses software to enhance token response to known physical attacks. Our approach draws on machine learning. We propose a variant of linear discriminant analysis (LDA), called PUF LDA, which reduces noise levels in PUF instances while enhancing changes from known attacks. We compare PUF LDA with standard techniques using an optical coating PUF and the following feature types: raw pixels, fast Fourier transform, short-time Fourier transform, and wavelets. We measure the true positive rate for valid detection at a 0% false positive rate (no mistakes on samples taken after an attack). PUF LDA improves the true positive rate from 50% on average (with a large variance across PUFs) to near 100%. While a well-designed physical process is irreplaceable, PUF LDA enables system designers to improve the PUF reliability-security tradeoff by incorporating attacks without redesigning the hardware token.
Starting Page	88
Ending Page	92
File Size	663655
Page Count	5
File Format	PDF
e-ISBN	9781479941124
DOI	10.1109/HST.2014.6855575
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Entropy Software Security Coatings Standards Principal component analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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