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2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

2012 IEEE International Symposium on Hardware-Oriented Security and Trust

2011 IEEE International Symposium on Hardware-Oriented Security and Trust

2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)

Entropy-based power attack

Low voltage fault attacks to AES

Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach

Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments

Using multiple processors in a single reconfigurable fabric for high-assurance applications

Side-channel based watermarks for integrated circuits

Multiplexing methods for power watermarking

Provably secure obfuscation of diverse watermarks for sequential circuits

FPGA implementations of the Hummingbird cryptographic algorithm

ExCCel: Exploration of complementary cells for efficient DPA attack resistivity

Trusted RTL: Trojan detection methodology in pre-silicon designs

Prototyping platform for performance evaluation of SHA-3 candidates

A comparison of power-analysis-resistant digital circuits

SLICED: Slide-based concurrent error detection technique for symmetric block ciphers

State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures

Efficient one-pass entity authentication based on ECC for constrained devices

A large scale characterization of RO-PUF

LISA: Maximizing RO PUF's secret extraction

Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses

Sensor physical unclonable functions

Current flattening circuit for DPA countermeasure

Side-channel attack resistant ROM-based AES S-Box

Hardware implementations of hash function Luffa

Entropy extraction in metastability-based TRNG

2009 IEEE International Workshop on Hardware-Oriented Security and Trust

2008 IEEE International Workshop on Hardware-Oriented Security and Trust

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in