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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nekooei, A. Navabi, Z. |
| Copyright Year | 2015 |
| Description | Author affiliation: Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran (Nekooei, A.; Navabi, Z.) |
| Abstract | Test time reduction is an important objective in SoC testing. This becomes harder to achieve when power management techniques, like dynamic voltage scaling, are used, that requires a core to be tested for all its operating voltages. Coupling test time with test power consumption, due to long interconnects and switching power consumption, creates a difficult situation for SoC testing. To cope with this issue, this paper proposes a new Test Access Mechanism (TAM) that uses Multi-Valued Logic (MVL). In this structure, test data going to cores with MVL technique through the same test bus. This paper proposes Binary-MVL converters, and structure of test data on a multi-voltage test bus. This arrangement also reduces test time in multi-VDD SoCs as well. We have analyzed on crosstalk noise, area and power overhead of the proposed structure. In addition, we use IEEE 1450 - Standard Test Interface Language (STIL) to send and receive MVL signal in the Automatic Test Equipment (ATE) side. We also present a Mixed-Integer Linear Programming (MILP) model for optimal test scheduling based on our new TAM structure. Experimental results for ITC'02 benchmark highlight the effectiveness of the proposed structure. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 462572 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479919994 |
| DOI | 10.1109/DTIS.2015.7127351 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-04-21 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Multi-Valued Logic Power demand Crosstalk Bandwidth Test Access Mechanism Scheduling System-on-chip Delays SoCs Mathematical model Testing Test Time |
| Content Type | Text |
| Resource Type | Article |
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