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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kuroki, F. Takayama, K. Takeda, S. Yoneyama, T. |
| Copyright Year | 2009 |
| Description | Author affiliation: Tohoku Institute of Technology, 6 Futatu-Sawa, Taihaku-Ku, Sendai, 9828588, Japan (Yoneyama, T.) || Kure National College of Technology, 2-2-11, Aga-Minami, 7378506, Japan (Kuroki, F.; Takayama, K.; Takeda, S.) |
| Abstract | A technique to reduce the range finding error in the NRD-guide pulse radar system was proposed for tank level sensor applications at 60 GHz. The considerable sensing error to be ± 15 cm, which was bigger than the theoretical one, was measured in the first range finding test. It was predicted that the measured error was due to clocks generated in a PLL embedded into an FPGA for the radar signal processing, so that a VCXO (Voltage Controlled Crystal Oscillator) with high stability performance was employed to overcome such difficulty. Based on the upgraded radar signal processing, we could successfully decrease the measured error to be within ± 2cm. |
| Starting Page | 266 |
| Ending Page | 269 |
| File Size | 317405 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424447473 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-09-30 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Subject Keyword | Voltage-controlled oscillators Signal generators Radar signal processing Radar applications Error correction Level control Phase locked loops Field programmable gate arrays Testing Clocks |
| Content Type | Text |
| Resource Type | Article |
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