NDLI: Low Power Behavioral Synthesis

Content Provider	IEEE Xplore Digital Library
Author	Guan-Jun Wang Ying Zhao
Copyright Year	2009
Abstract	In this paper, a framework for reducing power during behavioral synthesis is proposed. A new parameter called Cycle Power Product (CPP) is defined which captures the power characteristics as an equally weighted sum of normalized mean cycle power. To minimize this parameter uses multiple supply voltages and dynamic frequency clocking and results in reduction of both energy and transient power. The cycle differential power can be modeled either as the mean deviation from the average power or as the cycle-to-cycle power gradient. The switching activity information is obtained from behavioral simulations. Based on the above we develop a new datapath scheduling algorithm which attempts at power and energy minimization by minimizing the CPP parameter during the scheduling process. The type and number of functional units available becomes the set of resource constraints for the scheduler. Experimental results indicate that the scheduler that minimizes CPP instead of conventional energy or average power as objective function could achieve significant reductions in power and energy.
Starting Page	160
Ending Page	163
File Size	130070
Page Count	4
File Format	PDF
ISBN	9781424467549
e-ISBN	9781424467556
DOI	10.1109/ICICSE.2009.74
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Fluctuations low power design behavioral synthesis Minimization Batteries Scheduling algorithm Concurrent computing cycle power product Voltage Capacitance Circuit synthesis Clocks
Content Type	Text
Resource Type	Article

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