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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shahabuddin, S. Janhunen, J. Suikkanen, E. Steendam, H. Juntti, M. |
| Copyright Year | 2014 |
| Description | Author affiliation: Dept. of Commun. Eng., Univ. of Oulu, Oulu, Finland (Shahabuddin, S.; Janhunen, J.; Suikkanen, E.; Juntti, M.) || Dept. of Telecommun. & Inf. Process., Ghent Univ., Ghent, Belgium (Steendam, H.) |
| Abstract | Cognitive radio (CR) systems require flexible and adaptive implementations of signal processing algorithms. An adaptive symbol detector is needed in the baseband receiver chain to achieve the desired flexibility of a CR system. This paper presents a novel design of an adaptive detector as an application-specific instruction-set processor (ASIP). The ASIP template is based on transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed to support different suboptimal multiple-input multiple-output (MIMO) detection algorithms in a single TTA processor. The linear minimum mean-square error (LMMSE) and three variants of the selective spanning for fast enumeration (SSFE) detection algorithms are considered. The detection algorithm can be switched between the LMMSE and SSFE according to the bit error rate (BER) performance requirement in the TTA processor. The design can be scaled for different antenna configurations and different modulations. Some of the algorithm architecture co-optimization techniques used here are also presented. Unlike most other detector ASIPs, high level language is used to program the processor to meet the time-to-market requirements. The adaptive detector delivers 4.88-49.48 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology. |
| Starting Page | 305 |
| Ending Page | 310 |
| File Size | 429931 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781631900037 |
| DOI | 10.4108/icst.crowncom.2014.255419 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-06-02 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | ICST |
| Subject Keyword | Bit error rate Detectors Throughput Vectors Matrix decomposition Detection algorithms Clocks |
| Content Type | Text |
| Resource Type | Article |
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