NDLI: Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Hapsari, E.Y. Kumar, R. Sheu, G. Shao-Ming Yang Anil, T.V.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Asia Univ., Taichung, Taiwan (Hapsari, E.Y.; Kumar, R.; Sheu, G.; Shao-Ming Yang; Anil, T.V.)
Abstract	The evolution of Bipolar CMOS DMOS (BCD) technology leads in the improvement of design technology to produce better device performance with fabrication cost effectiveness as concerned. In this paper, 0.18μm BCD technology with linear p-top layer N-channel LDMOS structure from 20V to 60V is presented with best in class Ron for both N-channel and P-channel LDMOS compared to recent BCD technology works. The optimization of current gain of 20V BJT has been done by adjustment of emitter width and boron doping concentration of base with increasing of current gain up to ten times higher without significantly change the breakdown voltage.
Starting Page	16
Ending Page	19
File Size	1156832
Page Count	4
File Format	PDF
ISBN	9781479933860
e-ISBN	9781479933877
DOI	10.1109/NMDC.2013.6707471
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Electric breakdown CMOS technology CMOS integrated circuits Current density MOS devices
Content Type	Text
Resource Type	Article

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Process integration of best in class specific-on resistance of 20V to 60V 0.18µm bipolar CMOS DMOS technology