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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Landernas, K. Holmberg, J. |
| Copyright Year | 2005 |
| Description | Author affiliation: Dept. of Comput. Sci. & Electron., Malardalen Univ., Vasteras, Sweden (Landernas, K.; Holmberg, J.) |
| Abstract | In this paper, the performance of high-speed digit-serial processing elements for recursive systems is studied. A 6th-order LDI allpass filter has been implemented using digit-serial arithmetics, where two implementation cases are studied. In Implementation Case I the digit-serial processing elements are realized using unfolding (Parhi, 1991), which is the most common design method in digit-serial processing, and in Case 2 processing elements that can be pipelined to the hit-level are utilized. The filter realizations are implemented using a 0.18 /spl mu/m standard cell technology. The studied properties are throughput and current consumption. It is concluded that implementing the filters using processing elements that can be pipelined to the bit-level results in a higher throughput. This is, however, at the expense of significantly higher current consumption. The throughput is on average 44% higher for Implementation Case 2 compared to Implementation Case 1. The difference in current consumption is on average 72%. |
| File Size | 138149 |
| File Format | |
| ISBN | 0780390660 |
| DOI | 10.1109/ECCTD.2005.1523107 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-09-02 |
| Publisher Place | Ireland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer science Energy consumption Design methodology Lattices Chebyshev approximation Throughput Frequency Digital filters Delay Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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