NDLI: Formal design and verification of on chip networking

Content Provider	IEEE Xplore Digital Library
Author	Sammane, G.A. Schmaltz, J. Borrione, D.
Copyright Year	2004
Description	Author affiliation: VDS Group, TIMA Lab., Grenoble, France (Sammane, G.A.; Schmaltz, J.; Borrione, D.)
Abstract	In this paper the formal design of networks and verification of on chip networking is presented in this paper. Basic octagon architecture with bidirectional links is demonstrated for this analysis. An octagon packet is the data that must be carried from the source node to the destination node. A network on chip model, written in a standard design language (VHDL) and the behavior is simulated on traffic hypotheses. An assertion-based verification in TheoSim is used to prove the expression satisfies the properties. The method is supported by a combination of simulation and symbolic reasoning engines that bridges the gap between specification and implementation debugging.
Sponsorship	Syriatel Global Commun. Syrian Comput. Soc. Network HAMSHO Int. Phoenix Consulting DETECON: Detecon & Diebold Consultants Republique Francaise Ambassade de France en Syrie Syrian Airlines STE JUCI
Starting Page	657
Ending Page	658
File Size	189308
Page Count	2
File Format	PDF
ISBN	0780384822
DOI	10.1109/ICTTA.2004.1307937
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-23
Publisher Place	Syria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Productivity Computational modeling Network-on-a-chip Laboratories Traffic control Routing Computer networks Telecommunication computing Distributed computing Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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