NDLI: Regular 2D NASIC-based architecture and design space exploration

Content Provider	IEEE Xplore Digital Library
Author	Teodorov, C. Narayanan, P. Lagadec, L. Dezan, C.
Copyright Year	2011
Description	Author affiliation: Lab-STICC CNRS UMR 3192, Université de Bretagne Occidentale, Brest, France (Teodorov, C.; Lagadec, L.; Dezan, C.) \|\| Nanoscale Computing Fabrics Laboratory, University of Massachusetts, Amherst, USA (Narayanan, P.)
Abstract	As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
Starting Page	70
Ending Page	77
File Size	2092048
Page Count	8
File Format	PDF
ISBN	9781457709937
e-ISBN	9781457709951
DOI	10.1109/NANOARCH.2011.5941486
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wires Computer architecture Programmable logic arrays Routing Fabrics Nanoscale devices CMOS integrated circuits
Content Type	Text
Resource Type	Article

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