NDLI: Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration

Content Provider	IEEE Xplore Digital Library
Author	Jie Luo Yilin Zhang Vadlamani, S. Byeong Kil Lee
Copyright Year	2012
Abstract	Early-stage design exploration requires the detailed simulation which is running applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite (e.g., SPEC CPU 2006) takes several weeks to months to complete. This problem has motivated several research groups to come up with methodologies to reduce simulation time while maintaining a certain level of accuracy. Among many techniques for reducing simulation time, a tool called Sim Point is popularly used. However, simulation load even with the reduced workloads is still heavy, considering design complexity of modern microprocessors. Basic motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would eliminate those simulation points from the simulation setup procedure. In this paper, we focus on identifying those simulation points which have high sensitivity or low sensitivity, by which overall simulation methodology can be effectively improved. We also performed the performance-sensitivity-based similarity analysis (grouping) among simulation points on specific performance metric which can be an overall performance metric or a component-level metric.
Starting Page	496
Ending Page	501
File Size	265271
Page Count	6
File Format	PDF
ISBN	9781467307987
DOI	10.1109/ITNG.2012.112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sensitivity Hidden Markov models Benchmark testing performance evaluation workload characterization Hardware Mathematical model early-stage design exploration Standards workload reduction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Performance-sensitivity and performance-similarity based workload reduction

Effective workload reduction for early-stage power estimation

Markovian Workload Characterization for QoS Prediction in the Cloud

Ergodic Continuous Hidden Markov Models for workload characterization

ArchRanker: A ranking approach to design space exploration

Hidden Markov model based automated fault localization for integration testing

A Reevaluation and Benchmark of Hidden Markov Models

Modeling Cross-Architecture Co-Tenancy Performance Interference

Periodic hidden Markov model-based workload clustering and characterization

Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration

Similar Documents

Performance-sensitivity and performance-similarity based workload reduction

Effective workload reduction for early-stage power estimation

Markovian Workload Characterization for QoS Prediction in the Cloud

Ergodic Continuous Hidden Markov Models for workload characterization

ArchRanker: A ranking approach to design space exploration

Hidden Markov model based automated fault localization for integration testing

A Reevaluation and Benchmark of Hidden Markov Models

Modeling Cross-Architecture Co-Tenancy Performance Interference

Periodic hidden Markov model-based workload clustering and characterization

Performance-Sensitivity-based Workload Tailoring for Effective Design Exploration