NDLI: The Apparatus and Enabling of a Code Balanced System

Content Provider	IEEE Xplore Digital Library
Author	Benavides, T. Treon, J. Weide Chang
Copyright Year	2007
Description	Author affiliation: Dept. of Comput. Sci., California State Univ., Sacramento, CA (Benavides, T.; Treon, J.; Weide Chang)
Abstract	Success in the embedded world revolves around two key concepts: cost effectiveness and performance. The ability for an operating system to boot quickly combined with speedy application usage at runtime is important with regards to consumer unit adoption. The most common memory sub-system setup in cellular phone architectures today is what is called an eXecute-In-Place architecture. This type of memory sub-system defines the execution of code and data directly from NOR flash memory. An additional memory architecture of choice is called a Store and Download architecture. This is a memory subsystem where the compressed code gets copied to RAM at boot time and executes out of the RAM. This paper explores the addition of a new memory usage model called a code balanced system. The result is a system that combines a small RAM memory requirement with a performance increase for improved targeted application and boot time execution
Sponsorship	Premier Hall for Sci. and Eng
Starting Page	1001
Ending Page	1007
File Size	586543
Page Count	7
File Format	PDF
ISBN	0769527760
DOI	10.1109/ITNG.2007.191
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Cellular phones Bills of materials Flash memory Memory architecture Random access memory Read-write memory Hardware Application software Delay
Content Type	Text
Resource Type	Article

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The Implementation of a Hybrid-Execute-In-Place Architecture to Reduce the Embedded System Memory Footprint and Minimize Boot Time

Cost-efficient memory architecture design of NAND flash memory embedded systems

A 133MHz 170mW 10/spl mu/A standby application processor for 3G cellular phones

Management policies for non-volatile write caches

RAMSES-FT: a fault simulator for flash memory testing and diagnostics

An Advanced Java Card System Architecture for Smart Card Based on Large RAM Memory

Current status and future directions of the ITRON Subproject

A vector memory system based on wafer-scale integrated memory arrays

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The Apparatus and Enabling of a Code Balanced System

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