NDLI: An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance

Content Provider	IEEE Xplore Digital Library
Author	Lodde, M. Flich, J.
Copyright Year	2013
Description	Author affiliation: Parallel Archit. Group, Univ. Politec. de Valencia, Valencia, Spain (Lodde, M.; Flich, J.)
Abstract	In future many-core chip systems, virtualization of chip resources will become mandatory in order to get the maximum chip utilization and provide the maximum possible service to demanding applications. Also, failures of the chip will need to be managed to keep high yields of chips manufacturing. In this paper we provide a novel substrate for the on-chip interconnect and for the memory coherence protocol. We take a radical approach when designing the network and memory, by effectively co-designing both. We take into account the visibility of the whole chip resources to the memory controller, which is in charge of providing the appropriate support for virtualization and memory-level fault-tolerance. Then, the network is designed taking into account the memory coherence protocol and providing solutions for the critical communication requirements of memory modules (caches) and processors in a virtualized domain. The coherence protocol is also designed in order to allow its effective use in a virtualized scenario. With our approach, the chip can be fully virtualized on application demand providing total partitioning of core resources and smart use of memory resources. Results demonstrate that our scheme effectively optimizes the utilization of chip resources, allowing the implementation of techniques which can outperform a first-touch policy up to a 6%, reducing LLC misses and enabling LLC fault tolerance.
Starting Page	1
Ending Page	8
File Size	887081
Page Count	8
File Format	PDF
ISBN	9781467364911
e-ISBN	9781467364935
e-ISBN	9781467364928
DOI	10.1109/NoCS.2013.6558410
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Tiles Fault tolerant systems Ports (Computers) Switches Coherence Routing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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