NDLI: Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation

Content Provider	IEEE Xplore Digital Library
Author	Navaridas, J. Khan, B. Khan, S. Faraboschi, P. Lujan, M.
Copyright Year	2012
Abstract	Architectural simulation is an essential tool when it comes to evaluating the design of future many-core chips. However, reproducing all the components of such complex systems precisely would require unreasonable amounts of computing power. Hence, a trade off between accuracy and compute time is needed. For this reason most state-of-the-art tools do not have accurate models for the networks-on-chip, and rely on timing models that permit fast-simulation. Generally, these models are very simplistic and disregard contention for the use of network resources. As the number of nodes in the network-on-chip grows, fluctuations with contention and other parameters can considerably affect the accuracy of such models. In this paper we present and evaluate a collection of timing models based on a reservation scheme which consider the contention for the use of network resources. These models provide results quickly while being more accurate than simple no-contention approaches.
Starting Page	91
Ending Page	98
File Size	1093928
Page Count	8
File Format	PDF
ISBN	9781467309738
DOI	10.1109/NOCS.2012.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-09
Publisher Place	Denmark
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Accuracy Computational modeling simulation Computer architecture Network-on-chip Benchmark testing performance evaluation Modelling Timing timing models Load modeling
Content Type	Text
Resource Type	Article

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